semiconductors:
Your career at capgemini

We are Capgemini Engineering, part of the Capgemini Group, and we are hiring Design-for-Testability (DFT) engineers with:
· 6+ years of hands-on experience in DFT and test flows using commercial EDA tools for large and complex SOCs.
· Profound knowledge of DFT techniques, including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500 Std., and MBIST/LBIST.
· Familiarity with leading EDA providers such as Synopsys DFT Complier, Tetramax, VCS, Tessent, and Modus/Encounter tool suite.
· Experience in RTL simulation, synthesis, linting, CDC and RDC checks, STA, DFT, and quality metrics is advantageous.
· Proficiency in Perl/Tcl/Python scripting.
· Excellent analytical and problem-solving abilities.

Get the Future You Want!

We are Capgemini Engineering, part of the Capgemini Group, and we are hiring Design Verification (DV) engineers with:
· A solid understanding of SystemVerilog, along with substantial experience in constrained random and coverage-driven verification using UVM/OVM.
· Proficiency in creating UVC components or sequences.
· Basic knowledge of at least two of the following: AHB/AXI, PCIe/CXL, USB, DDR, serial protocols, processor verification, etc. Senior-level positions and above require expertise in at least one protocol.
· Comfortable with updating existing verification environments for feature enhancements. (Having the ability to architect UVM-based test benches from scratch is highly advantageous.)
· Platform-agnostic when it comes to EDA simulation/debugging tools.
· Proficiency in Perl, TCL, and Python scripting.
· Domain expertise in one of the following areas is preferred for senior-level positions and above: CPU processors/servers, multimedia, automotive, Ethernet, mobile technologies.

Get the Future You Want!

We are Capgemini Engineering, part of the Capgemini Group, and we are hiring Physical Design (PD) engineers with:
· 8+ years (preferred) of experience in challenging RTL2GDSII work conducted on 10nm or below nodes, with designs containing 500k – 1million+ instances.
· Proficiency in using PnR and timing analysis CAD tools from Synopsys and/or Cadence.
· Good understanding of synthesis flow, DFT scan/coverage, and optimization.
· Excellent skills in floorplan, power plan, CTS, place, route, and timing closure.
· Proficiency in Perl/TCL/Python scripting and Makefile.
· Expertise in timing STA/PTSI – signal integrity closure, and ECO generation/implementation.
· Strong capabilities in EM/IR, DRC, LVS, ERC analysis, and fixing.
· Experience with sign-off tape-out closure work.
· Any experience in top-level activities like floor planning, pin assignment, and tape-out is advantageous.

Get the Future You Want!

We are Capgemini Engineering, part of the Capgemini Group, and we are hiring Register Transfer Level (RTL) engineers with:
· Over 8 years of experience in VLSI design.
· Bachelor’s or master’s degree in electrical or computer Engineering.
· Proficiency in Verilog/System Verilog or VHDL.
· Experience in defining microarchitecture and designing complex design units.
· Previous experience in SoC design.
· Proficiency in advanced design practices such as Lint, CDC, and Low Power Design.
· Familiarity with various backend tools including synthesis and STA.
· Knowledge of CPU (ARM, RISC-V, or x86) instruction set.
· Proficiency in Perl, C, Python scripting, and programming.
· Understanding of verification methodologies.
· Strong communication and interpersonal skills.

Get the Future You Want!