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Key responsibilities: 
Highly motivated and dynamic engineer able to adopt new technology quickly  
Understanding of advanced CMOS process nodes and SoC design flows  
Experience with tools for schematic entry, simulation, spice models, and IC production effects  
Proficient knowledge of UNIX/Linux and fluent English  
M.Sc.EE or equivalent degree in Electronics, Computer Science, or Electrical engineering 

Key responsibilities: 

Experience with state-of-the-art analog design tools  
Experience with different implementation technologies  
Understanding of advanced CMOS process nodes and SoC design flows  
Experience with tools for physical layout, schematic entry, and physical verification  
Proficient knowledge of UNIX/Linux and fluent English  
M. Sc. EE or equivalent degree in Electronics, Computer Science, or Electrical engineering 

Key responsibilities: 

Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST  
Closely work with the physical design team to resolve timing constraints/issues  
Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues  
Debug and improve important DFT KPIs: test coverage/pattern efficiency  
Hierarchical retargeting  
Silicon bring-up, diagnosis, and support for physical failure analysis 

Key responsibilities: 

Own verification of IPs and SoCs in prototype and SoC design environment 
Establish functional and performance benchmarks 
Lead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms 
IP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IPs/SoCs 
Hands-on experience using an industry-standard verification methodology (UVM/VMM) 
Hands-on experience with Verilog/System Verilog or VHDL skills 

Key responsibilities: 

Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)  
In depth Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning, and analysis, Scan re-ordering, placement, CTS, place, and route
Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)  
In charge of all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis, and fixes  
Be part of the overall Low Power solution development and implementation 
Develop/enhance timing-related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top level to block level)  
Complete multiple design cycles of high complexity with little supervision 

Key responsibilities: 

Register Transfer Level (RTL) has a multi-lateral spectrum of increasing complexity which involves a deep understanding of cutting-edge designs and technologies, methods, and developing flows and tools as necessary in support of the design process 
Own feasibility studies for defining the system architecture, requirements, and external interfaces 
Develop microarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out 
Perform RTL coding, Lint checks, CDC tests, and creating timing constraint files 
Work closely with Synthesis, STA, PD, and DFT teams to meet all functional requirements, performance, power, and area goals 
Develop flows and tools as necessary in support of design activities